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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_MMFR4, Memory Model Feature Register 4</h1><p>The ID_MMFR4 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implemented memory model and memory management support in AArch32 state.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_MMFR4 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_mmfr4_el1.html">ID_MMFR4_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_MMFR4 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_MMFR4 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">EVT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">CCIDX</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">LSM</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">HPDS</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">CnP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">XNX</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">AC2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0-1">SpecSEI</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">EVT, bits [31:28]</h4><div class="field">
      <p>Enhanced Virtualization Traps. If EL2 is implemented, indicates support for the <a href="AArch32-hcr2.html">HCR2</a>.{TTLBIS, TOCU, TICAB, TID4} traps. Defined values are:</p>
    <table class="valuetable"><tr><th>EVT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p><a href="AArch32-hcr2.html">HCR2</a>.{TTLBIS, TOCU, TICAB, TID4} traps are not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p><a href="AArch32-hcr2.html">HCR2</a>.{TOCU, TICAB, TID4} traps are supported. <a href="AArch32-hcr2.html">HCR2</a>.TTLBIS trap is not supported.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p><a href="AArch32-hcr2.html">HCR2</a>.{TTLBIS, TOCU, TICAB, TID4} traps are supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_EVT</span> implements the functionality identified by the values <span class="binarynumber">0b0001</span> and <span class="binarynumber">0b0010</span>.</p>
<p>If EL2 is not implemented supporting AArch32, the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p>In Armv8.2, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b0010</span>.</p>
<p>From Armv8.5, the permitted values are:</p>
<ul>
<li><span class="binarynumber">0b0000</span> when EL2 is not implemented or does not support AArch32.
</li><li><span class="binarynumber">0b0010</span> when EL2 is implemented and supports AArch32.
</li></ul></div><h4 id="fieldset_0-27_24">CCIDX, bits [27:24]</h4><div class="field">
      <p>Support for use of the revised CCSIDR format and the presence of the CCSIDR2 is indicated. Defined values are:</p>
    <table class="valuetable"><tr><th>CCIDX</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>32-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>64-bit format implemented for all levels of the CCSIDR, and the CCSIDR2 register is implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_CCIDX</span> implements the functionality identified by <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.3, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-23_20">LSM, bits [23:20]</h4><div class="field">
      <p>Indicates support for LSMAOE and nTLSMD bits in <a href="AArch32-hsctlr.html">HSCTLR</a> and <a href="AArch32-sctlr.html">SCTLR</a>. Defined values are:</p>
    <table class="valuetable"><tr><th>LSM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>LSMAOE and nTLSMD bits not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>LSMAOE and nTLSMD bits supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_LSMAOC</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.2, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-19_16">HPDS, bits [19:16]</h4><div class="field">
      <p>Hierarchical permission disables bits in translation tables. Defined values are:</p>
    <table class="valuetable"><tr><th>HPDS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Disabling of hierarchical controls not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Supports disabling of hierarchical controls using the <a href="AArch32-ttbcr2.html">TTBCR2</a>.HPD0, <a href="AArch32-ttbcr2.html">TTBCR2</a>.HPD1, and <a href="AArch32-htcr.html">HTCR</a>.HPD bits.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>As for value <span class="binarynumber">0b0001</span>, and adds possible hardware allocation of bits[62:59] of the Translation table descriptors from the final lookup level for <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> use.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_AA32HPD</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_HPDS2</span> implements the functionality added by the value <span class="binarynumber">0b0010</span>.</p>
<div class="note"><span class="note-header">Note</span><p>The value <span class="binarynumber">0b0000</span> implies that the encoding for <a href="AArch32-ttbcr2.html">TTBCR2</a> is <span class="arm-defined-word">UNDEFINED</span>.</p></div></div><h4 id="fieldset_0-15_12">CnP, bits [15:12]</h4><div class="field">
      <p>Common not Private translations. Defined values are:</p>
    <table class="valuetable"><tr><th>CnP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Common not Private translations not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Common not Private translations supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_TTCNP</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.2, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-11_8">XNX, bits [11:8]</h4><div class="field">
      <p>Support for execute-never control distinction by Exception level at stage 2. Defined values are:</p>
    <table class="valuetable"><tr><th>XNX</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Distinction between EL0 and EL1 execute-never control at stage 2 not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Distinction between EL0 and EL1 execute-never control at stage 2 supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_XNX</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>When <span class="xref">FEAT_XNX</span> is implemented:</p>
<ul>
<li>If all of the following conditions are true, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the value of ID_MMFR4.XNX is <span class="binarynumber">0b0000</span> or <span class="binarynumber">0b0001</span>:<ul>
<li><a href="AArch64-id_aa64mmfr1_el1.html">ID_AA64MMFR1_EL1</a>.XNX ==1.
</li><li>EL2 cannot use AArch32.
</li><li>EL1 can use AArch32.
</li></ul>

</li><li>If EL2 can use AArch32 then the only permitted value is <span class="binarynumber">0b0001</span>.
</li></ul></div><h4 id="fieldset_0-7_4">AC2, bits [7:4]</h4><div class="field">
      <p>Indicates the extension of the <a href="AArch32-actlr.html">ACTLR</a> and <a href="AArch32-hactlr.html">HACTLR</a> registers using <a href="AArch32-actlr2.html">ACTLR2</a> and <a href="AArch32-hactlr2.html">HACTLR2</a>. Defined values are:</p>
    <table class="valuetable"><tr><th>AC2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p><a href="AArch32-actlr2.html">ACTLR2</a> and <a href="AArch32-hactlr2.html">HACTLR2</a> are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p><a href="AArch32-actlr2.html">ACTLR2</a> and <a href="AArch32-hactlr2.html">HACTLR2</a> are implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8.0, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.2, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-3_0-1">SpecSEI, bits [3:0]<span class="condition"><br/>When FEAT_RAS is implemented:
                        </span></h4><div class="field">
      <p>Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches.</p>
    <table class="valuetable"><tr><th>SpecSEI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The PE never generates an SError interrupt due to an External abort on a speculative read.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>The PE might generate an SError interrupt due to an External abort on a speculative read.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-3_0-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing ID_MMFR4</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0010</td><td>0b110</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_MMFR4) || boolean IMPLEMENTATION_DEFINED "ID_MMFR4 trapped by HCR_EL2.TID3") &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_MMFR4) || boolean IMPLEMENTATION_DEFINED "ID_MMFR4 trapped by HCR.TID3") &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_MMFR4;
elsif PSTATE.EL == EL2 then
    R[t] = ID_MMFR4;
elsif PSTATE.EL == EL3 then
    R[t] = ID_MMFR4;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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